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www.lansdale.com ml145502 ml145503 ml145505 pcm codec?ilter mono?ircuit page 1 of 26 issue a legacy device: motorola mc145502, mc145503, mc145505 the ml145502, ml145503, and ml145505 are all per channel pcm codec?ilter mono?ircuits. these devices perform the voice digitization and reconstruction as well as the band limiting and smoothing required for pcm systems. the ml145503 is a general purpose device that is offered in a 16?in package. these are designed to operate in both syn- chronous and asynchronous applications and contain an on?hip preci- sion reference voltage. the ml145505 is a synchronous device offered in a 16?in dip and wide body soic package intended for instrument use. the ml145502 is the full?eatured device which presents all of the options of the chip. this device is packaged in a 22?in dip and a 28?in chip carrier package these devices are pin?or?in replacements for motorolas first genera- tion of mc14400/01/02/03/05 pcm mono?ircuits and are upwardly compatible with the mc14404/06/07 codecs and other industry standard codecs. they also maintain compatibility with motorolas family of mc33120 and mc3419 slic products. the ml1455xx family of pcm codec?ilter mono?ircuits utilizes cmos due to its reliable low?ower performance and proven capability for complex analog/digital vlsi functions. ml145502 ? 22 pin and 28 pin packages ? transmit bandpass and receive low?ass filter on?hip ? pin selectable mu?aw/a?aw companding with corresponding data format ? on?hip precision reference voltage (3.15 v) ? power dissipation of 50 mw, power?own of 0.1 mw at ? v ? automatic prescaler accepts 128 khz, 1.536, 1.544, 2.048, and 2.56 mhz for internal sequencing ? selectable peak overload voltages (2.5, 3.15, 3.78 v) ? access to the inverting input of the txi input operational amplifier ? variable data clock rates (64 khz to 4.1 mhz) ? complete access to the three terminal transmit input operational amplifiers ? an external precision reference may be used ml145503 ?similar to the ml145502 plus: ? 16?in dip and soic 16 packages ? complete access to the three terminal transmit input operational amplifiers ml145505 ?somewhat similar to ml145503 except: ? common 64 khz to 4.1 mhz transmit/receive data clock p dip 16 = ep plastic dip case 648 16 1 22 1 p dip 22 = wp plastic dip case 708 sog 16 = -5p sog package case 751g plcc 28 = -4p plcc package case 776 16 1 28 1 cross reference/ordering information motorola p dip 22 mc145502p ML145502WP plcc 28 mc145502fn ml145502-4p p dip 16 mc145503p ml145503ep so 16w mc145503dw ml145503-5p p dip 16 mc145505p ml145505ep so 16w mc145505dw ml145505-5p lansdale package note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle .
ml145502, ml145503, ml145505 lansdale semiconductor, inc. ml145502/03/05 pcm codec?ilter mono?ircuit block diagram rce rdc receive shift register d/a shared dac 1, 12, 16, 20 cci prescaler sequence and control transmit shift register cci msi v ls pdi tdd tde tdc 2.5 v ref rsi circuitry a/d frequency frequency frequency controlled by v ls rx 100 k (internal resistors) v dd v ss rxo rxg rxo v dd v ss v ag v ref rsi txi ?tx + tx rx rx 400 a rdd + + + 1 notes: www.lansdale.com page 2 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. pin assignments (drawings do not reflect relative size) 5 4 3 2 1 10 9 8 7 6 11 14 15 16 17 18 19 20 13 21 22 12 + tx rxg rxo v ag v ref ?tx txi rxo v ss pdi mu/a rdc rce rdd v dd rsi msi tde tdd v ls cci ML145502WP ml145503ep ml145505ep ml145503-5p ml145505-5p 28?in pqlcc (top view) tdc 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 rdc rce rdd v ls tde tdd txi + tx rxo v ss pdi mu/a ?tx v ag v dd tdc 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 dclk rce rdd v ls tde tdd txi + tx rxo v ss pdi mu/a ?tx v ag v dd cci 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 rdc rce rdd v ls tde tdd txi + tx rxo v ss pdi mu/a ?tx v ag v dd tdc 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 dclk rce rdd v ls tde tdd txi + tx rxo v ss pdi mu/a ?tx v ag v dd cci 4 3 2 1 28 27 26 8 7 6 10 9 11 5 19 21 22 20 23 24 25 12 13 14 15 16 17 18 + tx rxo rxg ?tx txi nc nc tdc rdc rce tdd cci nc nc a / u m i d p c n i s m e d t v s l v s s o x r c n i s r d d r v g a v f e r v d d nc = no connection ml145502-4p www.lansdale.com page 3 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. absolute maximum ratings (voltage referenced to v ss ) rating symbol value unit dc supply voltage v dd , v ss ?0.5 to 13 v voltage, any pin to v ss v ?0.5 to v dd + 0.5 v dc drain per pin (excluding v dd , v ss ) i 10 ma operating temperature range t a ?40 to + 85 c storage temperature range t stg ?85 to + 150 c recommended operating conditions (t a = ?40 to + 85 c) characteristic min typ max unit dc supply voltage dual supplies: v dd = ?v ss , (v ag = v ls = 0 v) single supply: v dd to v ss (v ag is an output, v ls = v dd or v ss ) ml145502, ml145503, ml145505 (using internal 3.15 v reference) ml145502 using internal 2.5 v reference ml145502 using internal 3.78 v reference ml145502 using external 1.5 v reference, referenced to v ag 4.75 8.5 7.0 9.5 4.75 5.0 6.3 12.6 12.6 12.6 12.6 v power dissipation cmos logic mode (v dd to v ss = 10 v, v ls = v dd ) ttl logic mode (v dd = + 5 v, v ss = ?5 v, v ls = v ag = 0 v) 40 50 70 90 mw power down dissipation 0.1 1.0 mw frame rate transmit and receive 7.5 8.0 8.5 khz data rate ml145503 must use one of these frequencies, relative to msi frequency of 8 khz 128 1536 1544 2048 2560 khz data rate for ml145502, ml145505 64 4096 khz full scale analog input and output level ml145503, ml145505 ml145502 (v rsi = v ) ref = v ss dd rsi = v ss rsi = v ag ml145502 using an external reference v oltage applied at v ref pin rsi = v dd rsi = v ss rsi = v ag 3.15 3.78 3.15 2.5 1.51 x v ref 1.26 x v ref v ref vp digital levels (v ss to v dd = 4.75 v to 12.6 v, t a = ?40 to + 85 c) characteristic symbol min max unit input voltage levels (tde, tdc, rce, rdc, rdd, dc, msi, cci, pdi ) cmos mode (v ls = v dd , v ss is digital ground) ? ? ttl mode (v ls v dd ?4.0 v, v ls is digital ground) ? ? v il v ih v il v ih 0.7 x v dd v ls + 2.0 v 0.3 x v dd v ls + 0.8 v v output current for tdd (transmit digital data) cmos mode (v ls = v dd , v ss = 0 v and is digital ground) (v dd = 5 v, v out = 0.4 v) (v dd = 10 v, v out = 0.5 v) (v dd = 5 v, v out = 4.5 v) (v dd = 10 v, v out = 9.5 v) ttl mode (v ls v dd ?4.75 v, v ls = 0 v and is digital ground) (v ol = 0.4 v) (v oh = 2.4 v) i ol i oh i ol i oh 1.0 3.0 ?1.0 ?3.0 1.6 ?0.2 ma this device contains circuitry to protect against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applica- tion of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., v ss , v dd , v ls , or v ag ). www.lansdale.com page 4 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. analog transmission performance (v dd = + 5 v 5%, v ss = ?5 v 5%, v ls = v ag = 0 v, v ref = rsi = v ss (internal 3.15 v reference), 0 dbm0 = 1.546 vrms = + 6 dbm @ 600 , t a = ?40 to + 85 c, tdc = rdc = cc = 2.048 mhz, tde = rce = msi = 8 khz, unless otherwise noted) end?o?nd a/d d/a characteristic min max min max min max unit absolute gain (0 dbm0 @ 1.02 khz, t a = 25 c, v dd = 5 v, v ss = ?5 v) ?0.30 + 0.30 ?0.30 + 0.30 db absolute gain variation with temperature 0 to + 70 c 0.03 0.03 db absolute gain variation with temperature ?40 to +85 c 0.1 0.1 db absolute gain variation with power supply (v dd = 5 v, v ss = ?5 v, 5%) 0.02 0.02 db gain vs level tone (relative to ?10 dbm0, 1.02 khz) + 3 to ?40 dbm0 ?40 to ?50 dbm0 ?50 to ?55 dbm0 ?0.4 ?0.8 ?1.6 + 0.4 + 0.8 + 1.6 ?0.2 ?0.4 ?0.8 + 0.2 + 0.4 + 0.8 ?0.2 ?0.4 ?0.8 + 0.2 + 0.4 + 0.8 db gain vs level pseudo noise (a?aw relative to ?10 dbm0) ccitt g.714 ?10 to ?40 dbm0 ?40 to ?50 dbm0 ?50 to ?55 dbm0 ?0.25 ?0.30 ?0.45 + 0.25 + 0.30 + 0.45 ?0.25 ?0.30 ?0.45 + 0.25 + 0.30 + 0.45 db total distortion ?1.02 khz tone (c?essage) 0 to ?30 dbm0 ?40 dbm0 ?45 dbm0 35 29 24 36 29 24 36 30 25 dbc total distortion with pseudo noise (a?aw) ?3 dbm0 ccitt g.714 ?6 to ?27 dbm0 ?34 dbm0 ?40 dbm0 ?55 dbm0 27.5 35 33.1 28.2 13.2 28 35.5 33.5 28.5 13.5 28.5 36 34.2 30.0 15.0 db idle channel noise (for end?nd and a/d, see note 1) mu?aw, c?essage weighted a?aw, psophometric weighted 15 ?69 15 ?69 9 ?78 dbrnc0 dbm0p frequency response (relative to 1.02 khz @ 0 dbm0) 15 to 60 hz 300 to 3000 hz 3400 hz 4000 hz 4600 hz ?0.3 ?1.6 ?23 + 0.3 0 ?28 ?60 ?0.15 ?0.8 ?23 + 0.15 0 ?14 ?32 ?0.15 ?0.8 0.15 + 0.15 0 ?14 ?30 db inband spurious (1.02 khz @ 0 dbm0, transmit and rxo) 300 to 3000 hz ?43 ?43 dbm0 out?f?and spurious at rxo (300 ?3400 hz @ 0 dbm0 in) 4600 to 7600 hz 7600 to 8400 hz 8400 to 100,000 hz ?30 ?40 ?30 ?30 ?40 ?30 db idle channel noise selective @ 8 khz, input = v ag , 30 hz bandwidth ?70 ?70 dbm0 absolute delay @ 1600 hz (tdc = 2.048 mhz, tde = 8 khz) 310 180 s group delay referenced to 1600 hz (tdc = 2048 khz, tde = 8 khz) 500 to 600 hz 600 to 800 hz 800 to 1000 hz 1000 to 1600 hz 1600 to 2600 hz 2600 to 2800 hz 2800 to 3000 hz 200 140 70 40 75 110 170 ?40 ?40 ?30 ?20 90 120 160 s crosstalk of 1020 hz @ 0 dbm0 from a/d or d/a (note 2) ?75 ?80 db intermodulation distortion of two frequencies of amplitudes ?4 to ?21 dbm0 from the range 300 to 3400 hz ?41 ?41 db notes: 1. extrapolated from a 1020 hz @ ?50 dbm0 distortion measurement to correct for encoder enhancement. 2. selectively measured while the a/d is stimulated with 2667 hz @ ?50 dbm0. www.lansdale.com page 5 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. analog electrical characteristics (v dd = ?v ss = 5 v to 6 v 5%, t a = ?40 to + 85 c) characteristic symbol min typ max unit input current +tx, ?x i in 0.01 0.2 a ac input impedance to v ag (1 khz) +tx, ?x z in 5 10 m input capacitance +tx, ?x 10 pf input offset voltage of txl op amp < 30 mv input common mode voltage range +tx, ?x v icr v ss + 1.0 v dd ?2.0 v input common mode rejection ratio +tx, ?x cmrr 70 db txl unity gain bandwidth r l 10 k bw p 1000 khz txl open loop gain r l 10 k a vol 75 db equivalent input noise (c?essage) between +tx and ?x, at txl ?20 dbrnc0 output load capacitance for txl op amp 0 100 pf output voltage range txl op amp, rxo or rxo r l = 10 k to v ag r l = 600 to v ag v out v ss + 0.8 v ss + 1.5 v dd ?1.0 v dd ?1.5 v output current txl, rxo, rxo v ss + 1.5 v v out v dd ?1.5 v 5.5 ma output impedance rxo, rxo * 0 to 3.4 khz z out 3 output load capacitance for rxo and rxo * 0 200 pf output dc offset voltage referenced to v ag pin rxo rxo * 100 150 mv internal gainsetting resistors for rxg to rxo and rxo 62 100 225 k external reference voltage applied to v ref (referenced to v ag ) 0.5 v dd ?1.0 v v ref input current 20 a v ag output bias voltage 0.53 v dd + 0.47 v ss v v ag output current source sink i vag 0.4 10.0 0.8 ma output leakage current during power down for the txl op amp, v ag , rxo, and rxo 30 a positive power supply rejection ratio, transmit 0 ?100 khz @ 250 mv, c?essage weighting receive 45 55 50 65 dbc negative power supply rejection ratio, transmit 0 ?100 khz @ 250 mv, c?essage weighting receive 50 50 55 60 dbc * assumes that rxg is not connected for gain modifications to rxo . www.lansdale.com page 6 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. mode control logic (v ss to v dd = 4.75 v to 12.6 v, t a = ?40 to + 85 c) characteristic min typ max unit v ls voltage for ttl mode (ttl logic levels referenced to v ls ) v ss v dd ?4.0 v v ls voltage for cmos mode (cmos logic levels of v ss to v dd ) v dd ?0.5 v dd v mu/a select voltage mu?aw mode sign magnitude mode a?aw mode v dd ?0.5 v ag ?0.5 v ss v dd v ag + 0.5 v ss + 0.5 v rsi voltage for reference select input (ml145502) 3.78 v mode 2.5 v mode 3.15 v mode v dd ?0.5 v ag ?0.5 v ss v dd v ag + 0.5 v ss + 0.5 v v ref voltage for internal or external reference (ml145502 only) internal reference mode external reference mode v ss v ag + 0.5 v ss + 0.5 v dd ?1.0 v analog test mode frequency, ms = cci (ml145502 only) see pin description; test modes 128 khz switching characteristics (v ss to v dd = 9.5 v to 12.6 v, t a = ?40 to + 85 c, c l = 150 pf, cmos or ttl mode) characteristic symbol min typ max unit output rise time tdd output fall time t tlh t thl 30 30 80 80 ns input rise time tde, tdc, rce, rdc, dc, msi, cci input fall time t tlh t thl 4 4 s pulse width tde low, tdc, rce, rdc, dc, msi, cci t w 100 ns dclk pulse frequency (ml145502/05 only) tdc, rdc, dc f cl 64 4096 khz cci clock pulse frequency (msi = 8 khz) cci is internally tied to tdc on the ml145503, therefore, the transmit data clock must be one of these frequencies. this pin will accept one of these discrete clock frequencies and will compensate to produce internal sequencing. f cl1 f cl2 f cl3 f cl4 f cl5 128 1536 1544 2048 2560 khz propagation delay time tde rising to tdd low impedance ttl cmos tde falling to tdd high impedance ttl cmos tdc rising edge to tdd data, during tde high ttl cmos tde rising edge to tdd data, during tdc high ttl cmos t p1 t p2 t p3 t p4 90 90 90 90 90 90 180 150 55 40 180 150 180 150 ns tdc falling edge to tde rising edge setup time t su1 20 ns tde rising edge to tdc falling edge setup time t su2 100 ns tde falling edge to tdc rising edge to preserve the next tdd data t su8 20 ns rdc falling edge to rce rising edge setup time t su3 20 ns rce rising edge to rdc falling edge setup time t su4 100 ns rdd valid to rdc falling edge setup time t su5 60 ns cci falling edge to msi rising edge setup time t su6 20 ns msi rising edge to cci falling edge setup time t su7 100 ns rdd hold time from rdc falling edge t h 100 ns tde, tdc, rce, rdc, rdd, dc, msi, cci input capacitance 10 pf tde,tdc, rce, rdc, rdd, dc, msi, cci input current 0.01 10 a tdd capacitance during high impedance (tde low) 12 15 pf tdd input current during high impedance (tde low) 0.1 10.0 a www.lansdale.com page 7 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. d e vic e d e scri p tions a codecfilter is a device which is used for digitizing and recon- structing the human voice. these devices were developed primarily for the telephone network to facilitate voice switching and trans- mission. once the voice is digitized, it may be switched by digital switching methods or transmitted long distance (t1, microwave, satellites, etc.) without degradation. the name codec is an acronym from coder for the a/d used to digitize voice, and decoder for the d/a used for reconstructing voice. a codec is a single device that does both the a/d and d/a conversions. to digitize intelligible voice requires a signal to distortion of about 30 db for a dynamic range of about 40 db. this may be accomplished with a linear 13bit a/d and d/a, but will far exceed the required signal to distortion at amplitudes greater than 40 db below the peak amplitude. this excess performance is at the expense of data per sample. two methods of data reduction are implemented by compressing the 13bit linear scheme to compand- ed 8bit schemes. these companding schemes follow a segmented or piecewiselinearcurve formatted as sign bit, three chord bits, and four stepbits. for a given chord, all 16 of the steps have the same voltage weighting. as the voltage of the analog input increas- es, the four step bits increment and carry to the three chord bits which increment. with the chord bits incremented, the step bits double their voltage weighting. this results in an effective resolu- tion of 6bits (sign + chord + four step bits) across a 42 db dynam- ic range (7 chords above zero, by 6 db per chord). there are two companding schemes used; mu255 law specifically in north america, and alaw specifically in europe. these companding schemes are accepted worldwide. the tables show the linear quanti- zation levels to pcm words for the two companding schemes. in a sampling environment, nyquist theory says that to properly sample a continuous signal, it must be sampled at a frequency high- er than twice the signals highest frequency component. voice con- tains spectral energy above 3 khz, but its absence is not detrimental to intelligibility. to reduce the digital data rate, which is proportion- al to the sampling rate, a sample rate of 8 khz was adopted, consis- tent with a band-width of 3 khz. this sampling requires a lowpass filter to limit the high frequency energy above 3 khz from distort- ing the inband signal. the telephone line is also subject to 50/60 hz power line coupling which must be attenuated from the signal by a highpass filter before the a/d converter. the d/a process recon- structs a staircase version of the desired inband signal which has spectral images of the in-band signal modulated about the sample frequency and its harmonics. these spectral images are called alias- ing components which need to be attenuated to obtain the desired signal. the lowpass filter used to attenuate filter aliasing compo- nents is typically called a reconstruction or smoothing filter. the ml1455xx series pcm codecfilters have the codec, both presampling and reconstruction filters, a precision voltage refer- ence on chip, and require no external components. there are three distinct versions of the lansdale ml1455xx series. ml145502 the ml145502 pcm codecfilter is the full feature 22pin device. it is intended for use in applications requiring maximum flexibility. the ml145502 is intended for bit interleaved or byte interleaved applications with data clock frequencies which are non- standard or time varying. one of the five standard frequencies (see ml145503 below) is applied to the cci input, and the data clock inputs can be any frequency between 64 khz and 4.096 mhz. the v ref pin allows for use of an external shared reference or selection of the internal reference. the rxg pin accommodates gain adjust- ments for the inverted analog output. all three pins of the input gainsetting operational amplifier are present, providing maximum flexibility for the analog interface. ml145503 the ml145503 pcm codecfilter is intended for standard byte interleaved synchronous or asynchronous applications. tdc can be one of five discrete frequencies . these are 128 khz (40 to 60% duty cycle), 1.536, 1.544, 2.048, or 2.56 mhz. (for other data clock frequencies, see ml145502 or ml145505.) the internal ref- erence is set for 3.15 v peak full scale, and the full scale input level at txl and output level at rxo is 6.3 v peaktopeak. this is the + 3 dbm0 level of the pcm codecfilter. the +tx and tx inputs provide maximum flexibility for analog interface. all other func- tions are described in the pin description. ml145505 the ml145505 pcm codecfilter is intended for byte inter- leaved synchronous applications. the ml145505 has all the fea- tures of the ml145503 but internally connects tdc and rdc (see pin description) to the dc pin. one of the five standard frequencies (listed above) should be applied to cci. the data clock input (dc) can be any frequency between 64 khz and 4.096 mhz. www.lansdale.com page 8 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. p in d e scri p tions digital vls logic level select input and ttl digital ground vls controls the logic levels and digital ground reference for all digital inputs and the digital output. these devices can operate with logic levels from full supply (v ss to v dd ) or with ttl logic levels using v ls as digital ground. for v ls = v dd , all i/o is full supply (v ss to v dd swing) with cmos switch points. for v ss < v ls < (v dd 4 v), all inputs and outputs are ttl compatible with v ls being the digital ground. the pins controlled by v are inputs msi, cci, tde, tdc, rce, rdc, rdd, pdi, and output tdd. msi master synchronization input msi is used for determining the sample rate of the transmit side and as a time base for selecting the internal prescale divider for the convert clock input (cci) pin. the msi pin should be tied to an 8 khz clock which may be a frame sync or system sync signal. msi has no relation to transmit or receive data timing, except for determining the internal trans- mit strobe as described under the tde pin description. msi should be derived from the transmit timing in asynchronous applications. in many applications msi can be tied to tde. (msi is tied internally to tde in ml145503/05.) cci convert clock input cci is designed to accept five discrete clock frequencies. these are 128 khz, 1.536 mhz, 1.544 mhz, 2.048 mhz, or 2.56 mhz. the frequency at this input is compared with msi and prescale divided to produce the internal sequencing clock at 128 khz (or 16 times the sampling rate). the duty cycle of cci is dictated by the minimum pulse width except for 128 khz, which is used directly for internal sequencing and must have a 40 to 60% duty cycle. in asynchronous applications, cci should be derived from transmit timing. (cci is tied internally to tdc in ml145503.) tdc transmit data clock input tdc can be any frequency from 64 khz to 4.096 mhz, and is often tied to cci if the data rate is equal to one of the five discrete frequencies. this clock is the shift clock for the trans- mit shift register and its rising edges produce successive data bits at tdd. tde should be derived from this clock. (tdc and rdc are tied together internally in the ml145505 and are called dc.) cci is internally tied to tdc on the ml145503. therefore, tdc must satisfy cci timing requirements also. td e transmit data e nable input tde serves three major functions. the first tde rising edge following an msi rising edge generates the internal transmit strobe which initiates an a/d conversion. the inter- nal transmit strobe also transfers a new pcm data word into the transmit shift register (sign bit first) ready to be output at tdd. the tde pin is the high impedance control for the transmit digital data (tdd) output. as long as this pin is high, the tdd output stays low impedance. this pin also enables the output shift register for clocking out the 8bit serial pcm word. the logical and of the tde pin with the tdc pin- clocks out a new data bit at tdd. tde should be held high for eight consecutive tdc cycles to clock out a complete pcm word for byte interleaved applications. the transmit shift register feeds back on itself to allow multiple reads of the transmit data. if the pcm word is clocked out once per frame in a byte interleaved system, the msi pin function is transpar- ent and may be connected to tde. the tde pin may be cycled during a pcm word for bit interleaved applications. tde controls both the high imped- ance state of the tdd output and the internal shift clock. tde must fall before tdc rises (t su8 ) to ensure integrity of the next data bit. there must be at least two tdc falling edges between the last tde rising edge of one frame and the first tde rising edge of the next frame. msi must be available separate from tde for bit interleaved applications. tdd transmit digital data output the output levels at this pin are controlled by the v ls pin. for v ls connected to v dd , the output levels are from v ss to v dd . for a voltage of v ls between v dd 4 v and v ss , the output levels are ttl compatible with v ls being the digital ground supply. the tdd pin is a threestate output controlled by the tde pin. the timing of this pin is controlled by tdc and tde. when in ttl mode, this output may be made highspeed cmos compatible using a pullup resistor. the data format (mulaw, alaw, or sign magnitude) is con- trolled by the mu/a pin. rdc receive data clock input rdc can be any frequency from 64 khz to 4.096 mhz. this pin is often tied to the tdc pin for applications that can use a common clock for both transmit and receive data trans- fers. the receive shift register is controlled by the receive clock enable (rce) pin to clock data into the receive digital data (rdd) pin on falling rdc edges. these three signals can be asynchronous with all other digital pins. the rdc input is internally tied to the tdc input on the ml145505 and called dc. rc e receive clock e nable input the rising edge of rce should identify the sign bit of a re- ceive pcm word on rdd. the next falling edge of rdc, after a rising rce, loads the first bit of the pcm word into the re- ceive register. the next seven falling edges enter the remain- der of the pcm word. on the ninth rising edge, the receive pcm word is transferred to the receive buffer register and the a/d sequence is interrupted to commence the decode process. in asynchronous applications with an 8 khz transmit sample rate, the receive sample rate should be between 7.5 and 8.5 khz. two receive pcm words may be decoded and analog summed each transmit frame to allow onchip conferencing. the two pcm words should be clocked in as two single pcm words, a minimum of 31.25 s apart, with a receive data clock of 512 khz or faster. www.lansdale.com page 9 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. rdd receive digital data input rdd is the receive digital data input. the timing for this pin is controlled by rdc and rce. the data format is determined by the mu/a pin. mu/a select this pin selects the companding law and the data format at tdd and rdd. mu/a = v dd ; mu255 companding d3 data format with zero code suppress mu/a = vag; mu255 companding with sign magnitude data format mu/a = vss; alaw companding with ccitt data format bit inversions p di p ower down input the power down input disables the bias circuitry and gates off all clock inputs. this puts the v ag , txl, rxo, rxo, and tdd outputs into a highimpedance state. the power dissipation is reduced to 0.1 mw when pdi is a low logic level. the circuit operates normally with pdi = v dd or with a logic high as defined by connection at v ls . tdd will not come out of high impedance for two msi cycles after pdi goes high. dclk data clock input in the ml145505, tdc and rdc are internally connected to dclk. analog v ag analog ground input/output p in v ag is the analog ground power supply input/output. all analog signals into and out of the device use this as their ground reference. each version of the ml1455xx pcm codecfilter family can pro- vide its own analog ground supply internally. the dc voltage of this internal supply is 6% positive of the midway between v dd and v ss . this supply can sink more than 8 ma but has a current source limited to 400 a.the output of this supply is internally connected to the analog ground input of the part. the node where this supply and the analog ground are connected is brought out to the v ag pin. in symmetric dual supply systems (5, 6, etc.), v ag may be exter- nally tied to the system analog ground supply. when rxo or rxo drive low impedance loads tied to v ag , a pullup resistor to v dd will be required to boost the source current capability if v ag is not tied to the supply ground. all analog signals for the part are refer- enced to v ag , including noise; therefore, decoupling capacitors (0.1 f) should be used from v dd to v ag and v ss to v ag . v ref p ositive voltage reference input (ml145502 only) the v ref pin allows an external reference voltage to be used for the a/d and d/a conversions. if v ref is tied to v ss , the internal ref- erence is selected. if v ref > v ag , then the external mode is selected and the voltage applied to v ref is used for generating the internal converter reference voltage. in either internal or external reference mode, the actual voltage used for conversion is multiplied by the ratio selected by the rsi pin. the rsi pin circuitry is explained under its pin description below. both the internal and external refer- ences are inverted within the pcm codecfilter for negative input voltages such that only one reference is required. e xternal mode in the external reference mode (v ref >v ag ), a 2.5 v reference like the mc1403 may be connected from v ref to v ag . a single external reference may be shared by tying together a number of v ref pins and v ag pins from different codecfilters. in special applications, the external reference voltage may be between 0.5 and 5 v. however, the reference voltage gain selection circuitry associated with rsi must be considered to arrive at the desired codecfilter gain. internal mode in the internal reference mode (v ref =v ss ), an internal 2.5 v reference supplies the reference voltage for the rsi circuitry. the v ref pin is functionally connected to v ss for the ml145503,and ml145505 pinouts. rsi reference select input (ml145502 only) the rsi input allows the selection of three different overload or fullscale a/d and d/a converter reference voltages independent of the internal or external reference mode. the rsi pin is a digital input that senses three different logic states: v ss , v ag , and v dd . for rsi = v ag , the reference voltage is used directly for the con- verters. the internal reference is 2.5 v. for rsi = v ss , the reference voltage is multiplied by the ratio of 1.26, which results in an internal converter reference of 3.15 v. for rsi = v dd , the reference voltage is multiplied by 1.51, which results in an internal converter reference of 3.78 v. the device requires a minimum of 1.0 v of headroom between the internal converter reference to v dd . v ss has this same absolute valued minimum, also measured from v ag pin. the vari- ous modes of operation are summarized in table 2. the rsi pin is functionally connected to v ss for the ml145503, and ml145505 pinouts. www.lansdale.com page 10 of 26 issue a code sign/ magnitude mu?aw a?aw (ccitt) + full scale 1111 1111 1000 0000 1010 1010 + zero 1000 0000 1111 1111 1101 0101 ?zero 0000 0000 0111 1111 0101 0101 ?full scale 0111 1111 0000 0010 0010 1010 0 1 2 3 4 5 6 7 sign bit chord bits step bits note: starting from sign magnitude, to change format: to mu?aw msb is unchanged (sign) invert remaining seven bits if code is 0000 0000, change to 0000 0010 (for zero code suppression) to a?aw msb is unchanged (sign) invert odd numbered bits ignore zero code suppression
ml145502, ml145503, ml145505 lansdale semiconductor, inc. rxo, rxo receive analog outputs these two complimentary outputs are generated from the out- put of the receive filter. they are equal in magnitude and out of phase. the maximum signal output of each is equal to the maxi- mum peak?o?eak signal described with the reference. if a 3.15 v reference is used with rsi tied to v ag and a + 3 dbm0 sine wave is decoded, the rxo output will be a 6.3 v peak?o?eak signal. rxo will also have an inverted signal out- put of 6.3 v peak?o?eak. external loads may be connected from rxo to rxo for a 6 db push?ull signal gain or from either rxo or rxo to v ag . with a 3.15 v reference each output will drive 600 to + 9 dbm. with rsi tied to v dd , each out- put will drive 900 to + 9 dbm. rxg receive output gain adjust (ml145502 only) the purpose of the rxg pin is to allow external gain adjust- ment for the rxo pin. if rxg is left open, then the output signal at rxo will be inverted and output at rxo. thus the push?ull gain to a load from rxo to rxo is two times the output level at rxo. if external resistors are applied from rxo to rxg (ri) and from rxg to rxo (rg), the gain of rxo can be set differ- ently from inverting unity. these resistors should be in the range of 10 k . the rxo output level is unchanged by the resistors and the rxo gain is approximately equal to minus rg/ri. the actual gain is determined by taking into account the internal resistors which will be in parallel to these external resistors. the internal resistors have a large tolerance, but they match each other very closely. this matching tends to minimize the effects of their tolerance on external gain configurations. the circuit for rxg and rxo is shown in the block diagram. txl transmit analog input txi is the input to the transmit filter. it is also the output of the transmit gain amplifiers of the ml145502/03/05. the txi input has an internal gain of 1.0, such that a +3 dbm0 signal at txi corresponds to the peak converter reference voltage as described in the v ref and rsi pin descriptions. for 3.15 v refer- ence, the + 3 dbm0 input should be 6.3 v peak?o?eak. +tx/?x p ositive tx amplifier input negative tx amplifier input the txl pin is the input to the transmit band?ass filter. if +tx or ?x is available, then there is an internal amplifier pre- ceding the filter whose pins are +tx, ?x, and txi. these pins allow access to the amplifier terminals to tailor the input gain with external resistors. the resistors should be in the range of 10 k . if +tx is not available, it is internally tied to v ag . if ?x and +tx are not available, the txi is a unity gain high?mpedance input. p ow e r su pp li e s v dd most p ositive p ower supply v dd is typically 5 to 12 v. v ss most negative p ower supply v ss is typically 10 to 12 v negative of v dd . for a ? v dual?upply system, the typical power supply con- figuration is v dd = + 5 v, v ss = ?5 v, v ls = 0 v (digital ground accommodating ttl logic levels), and v ag = 0 v being tied to system analog ground. for single?upply applications, typical power supply configu- rations include: v dd = 10 v to 12 v v ss = 0 v v ag generates a mid supply voltage for referencing all analog signals. v ls controls the logic levels. this pin should be connected to v dd for cmos logic levels from v ss to v dd . this pin should be connected to digital ground for true ttl logic levels refer- enced to v ls . t e sting consid e rations (ml145502 only) an analog test mode is activated by connecting msi and cci to 128 khz. in this mode, the input of the a/d (the output of the tx filter) is available at the pdi pin. this input is direct coupled to the a/d side of the codec. the a/d is a differential design. this results in the gain of this input being effectively attenuated by half. if monitored with a high?mpedance buffer, the output of the tx low?ass filter can also be measured at the pdi pin. this test mode allows independent evaluation of the transmit low?ass filter and a/d side of the codec. the transmit and receive channels of these devices are tested with the codec?ilter fully functional. www.lansdale.com page 11 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. figure 1. test circuit * to define rdd when tdd is high z. ml145503 v ag rxo + tx txi ?tx mu/a pdi v ss v dd rdd rce rdc tdc tdd tde v ls 1 2 3 4 5 6 7 89 10 11 12 13 14 16 15 600 5 k 10 k 681 v ag rx tx ?5 v clock enable 51 k * 5 v 0.1 f 0.1 f table 1. options available by pin selection rsi* pin level v ref * pin level peak?o?eak overload voltage (txl, rxo) v dd v ss 7.56 v p? v dd v ag + v ext (3.02 x v ext ) v p? v ag v ss 5 v p? v ag v ag + v ext (2 x v ext ) v p? v ss v ss 6.3 v p? v ss v ag + v ext (2.52 x v ext ) v p? * on ml145503/05, rsi and v ref tied internally to v ss . table 2. summary of operation conditions user programmed through pins v dd , v ag , and v ss pin programmed logic level mu/a rsi peak overload voltage v ls v dd mu?aw companding curve and d3/d4 digital formats with zero code suppress 3.78 cmos logic levels v ag mu?aw companding curve and sign magnitude data format 2.50 ttl levels v ag up v ss a?aw companding curve and ccitt digital format 3.15 ttl levels v ss up www.lansdale.com page 12 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. figure 2. transmit timing diagram * data output during this time will vary depending on tdc rate and tde timing. tde tdc t su2 t su1 1 2 3 t p1 t p4 f cl t w t w t su8 msb lsb tdd t p3 t p2 t p3 t p2 4 5 6 7 8 9 10 11 pcm word repeated * figure 3. receive timing diagram don? care rce rdc rdd lsb msb don? care 1 2 3 4 5 6 7 8 9 10 11 t w f cl t w t w t su5 t su4 t su3 t h figure 4. msi/cci timing diagram msi cci 1 2 3 4 5 6 7 8 9 10 11 t w t w t w t su7 t su6 www.lansdale.com page 13 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. figure 5. ml145502 gain vs level mu?aw transmit figure 6. ml145502 gain vs level mu?aw receive figure 7. ml145502 quantization distortion mu?aw transmit figure 8. ml145502 quantization distortion mu?aw receive figure 9. ml145502 gain vs level a?aw transmit figure 10. ml145502 gain vs level a?aw receive input level at 1.02 khz v dd = + 5 v v ss = ?5 v 2048 khz clock guaranteed performance typical peformance ?1.00 ?0.80 ?0.60 ?0.40 ?0.20 0 0.20 0.40 0.60 0.80 1.00 ) b d ( r o r r e n i a g input level at 1.02 khz v dd = + 5 v v ss = ?5 v 2048 khz clock guaranteed performance typical peformance 0 ?10 ?20 ?30 ?40 ?50 ?60 ?1.00 ?0.80 ?0.60 ?0.40 ?0.20 0 0.20 0.40 0.60 0.80 1.00 ) b d ( r o r r e n i a g input level at 1.02 khz c?essage weighted v dd = + 5 v v ss = ?5 v 2048 khz clock guaranteed performance typical peformance 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 t s i d n o i t z i t n a u q) b d ( n o i t r o input level at 1.02 khz c?essage weighted v dd = + 5 v v ss = ?5 v 2048 khz clock guaranteed performance typical peformance 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 t s i d n o i t z i t n a u q) b d ( n o i t r o typical peformance guaranteed performance v dd = + 5 v v ss = ?5 v 2048 khz clock ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 input level pseudo noise (dbm0) ) b d ( r o r r e n i a g ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 typical peformance guaranteed performance v dd = + 5 v v ss = ?5 v 2048 khz clock input level pseudo noise (dbm0) ) b d ( r o r r e n i a g 0 ?10 ?20 ?30 ?40 ?50 ?60 ?10 ?20 ?30 ?40 ?50 ?60 ?10 ?20 ?30 ?40 ?50 ?60 0 ?10 ?20 ?30 ?40 ?50 ?60 0 ?10 ?20 ?30 ?40 ?50 ?60 www.lansdale.com page 14 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. figure 11. ml145502 quantization distortion a?aw transmit figure 12. ml145502 quantization distortion a?aw receive figure 13. ml145502 power supply rejection ratio positive transmit vac = 250 mvrms, c?essage weighted figure 14. ml145502 power supply rejection ratio negative transmit vac = 250 mvrms, c?essage weighted figure 15. ml145502 power supply rejection ratio positive receive vac = 250 mvrms, c?essage weighted figure 16. ml145502 power supply rejection ratio negative receive vac = 250 mvrms, c?essage weighted psophometric weighted v dd = + 5 v v ss = ?5 v 2048 khz guaranteed performance typical performance input level pseudo noise (dbm0) 10.0 15.0 20.0 25.0 30.0 35.0 40.0 t s i d n o i t a z i t n a u q) b d ( n o i t r o psophometric weighted v dd = + 5 v v ss = ?5 v 2048 khz guaranteed performance typical performance input level pseudo noise (dbm0) 10.0 15.0 20.0 25.0 30.0 35.0 40.0 t s i d n o i t a z i t n a u q) b d ( n o i t r o frequency (khz) 100 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 typical performance l p p u s r e w o p) b d ( n o i t c e j e r y typical performance frequency (khz) 100 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 l p p u s r e w o p) b d ( n o i t c e j e r y typical performance frequency (khz) 100 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 l p p u s r e w o p ) b d ( n o i t c e j e r y typical performance frequency (khz) 100 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 l p p u s r e w o p ) b d ( n o i t c e j e r y 0 ?10 ?20 ?30 ?40 ?50 ?60 0 ?10 ?20 ?30 ?40 ?50 ?60 www.lansdale.com page 15 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. figure 17. ml145502 pass?and filter response transmit figure 18. ml145502 low?ass filter response transmit figure 19. ml145502 high?ass filter response transmit figure 20. ml145502 pass?and filter response receive figure 21. ml145502 low?ass filter response receive guaranteed performance typical performance frequency (khz) 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 ?18.0 ?16.0 ?14.0 ?12.0 ?10.0 ?8.0 ?6.0 ?4.0 ?2.0 0 2.0 guaranteed performance ) b d ( n i a g frequency (khz) typical performance guaranteed performance 3.6 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 ?0.8 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 ) b d ( n i a g typical performance guaranteed performance frequency (khz) 3.6 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0 ?0.8 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 ) b d ( n i a g typical performance frequency (khz) 0.24 0.20 0.16 0.12 0.08 0.04 0 ?30.0 ?26.0 ?22.0 ?18.0 ?14.0 ?10.0 ?6.0 ?2.0 2.0 guaranteed performance ) b d ( n i a g frequency (khz) guaranteed performance typical performance 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 ?18.0 ?16.0 ?14.0 ?12.0 ?10.0 ?8.0 ?6.0 ?4.0 ?2.0 0 2.0 guaranteed performance ) b d ( n i a g www.lansdale.com page 16 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. figure 22. simple clock circuit for driving ml145502/03/05 codec?ilters 2.048 mhz 8 khz 255 256 1 2 3 4 5 6 7 8 9 10 2.048 mhz (tdc, rdc, cci) 18 pf + 5 v + 5 v + 5 v v cc r osc in osc out 1 osc out 2 8 khz (tde, rce, msi) gnd q8 q4 gnd q jq k 1/2 mc74hc73 v cc 2.048 mhz 18 pf 300 10 m mc74hc4060 0.1 f 1/2 mc74hc73 r q jq k r www.lansdale.com page 17 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. 23a. simplified transformer hybrid using ml145503 note: hybrid balance by r5 and r6 to equate the rxo signal gain at txl through the inverting and non?nverting signal paths. 23b. universal transformer hybrid using ml145503 a v out = r0 r4 (r2 + r1) r3 + r0 r4 (r2 + r1) r3 + r0 r4 a v in = ?r1 r2 r0 n = 1 r0 n = 2 ?48 v n = 1 10 k 10 k v ag rxo + tx txi ?tx mu/a pdi v ss v ls tde tdd tdc rdc rce rdd v dd mc145503 r0 n = 1 r3 n = 2 ?48 v n = 1 r2 r1 v ag rxo + tx txi ?tx mu/a pdi v ss v ls tde tdd tdc rdc rce rdd v dd mc145503 r5 r6 r4 ? r0 r4 figure 23. hybrid interfaces to the ml145503 pcm codec?ilter mono?ircuit r0 = r3 r4 (r2 + r1) ? r3 r4 www.lansdale.com page 18 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. figure 24. hybrid interfaces to the ml145502 pcm codec?ilter mono?ircuit r1 r3 r6 2 r2 r4 r5 + r6 1 1 + = r0 = 600 r0 = 900 n = 1 n = 1 n = 2 r0 r5 r4 r3 r6 r0 r2 r1 ?48 v ss + v ref v ag rxo rxg rxo + tx txi ?tx mu/a pdi v ss v ls msi tde tdd cci tdc rdc rce rdd v dd rsi ml145502 note: balance by r5 and r6 to equate the txl gains through the inverting and non?nverting input signal paths, respectively, is given by: 24a. universal transformer hybrid using ml145502 tx gain = r1/r2 rx gain = 1 + r3/r4 r5, r6 10 k adjust rx gain with r3 adjust tx gain with r1 r1 r2 r3 r4 r5 r5 + r6 r0 10 k 24b. single?nded hybrid using ml145502 + v ref v ag rxo rxg rxo + tx txi ?tx mu/a pdi v ss v ls msi tde tdd cci tdc rdc rce rdd v dd rsi ml145502 n = 1 n = 1 ?48 20 k n = 2 20 k 10 k v ss r0 = 600 r0 = 900 r0 t r www.lansdale.com page 19 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. 3 0 5 5 4 1 l m l 1 9 1 4 3 c m v 5 + v 5 + v 5 v 0 5 + v 8 4 0 1 f p i t g n i r 7 4 0 0 . 0 2 0 0 4 n 1 1 1 1 p i t 5 2 1 p i t 7 4 0 0 . 0 7 4 0 0 . 0 2 0 0 4 n 1 v 8 4 5 7 k 6 . 9 1 k 7 4 1 . 0 k 1 5 7 k 6 . 9 1 1 2 3 4 5 6 7 8 9 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 v c c p e p b i s t c c i s r n b n e v e e i x r o x t i d p o s h o s t o s r t s h v g a v b q 7 4 . 0 7 4 . 0 1 r k 1 . 0 3 4 r k 6 . 9 1 3 r k 2 . 2 4 2 r k 3 4 1 5 r k 6 2 1 k 0 1 k 0 1 ) 0 a ( ) 1 a ( 1 . 0 6 1 5 1 4 1 3 1 2 1 1 1 0 1 1 2 3 4 5 6 7 9 8 1 . 0 v g a o x r x t + i x t x t a / u m i d p v s s v d d v s l d d r e c r c d r c d t d d t e d t 7 r k 0 7 2 figure 25. a complete single party channel unit using mc3419 slic and ml145503 pcm mono?ircuit www.lansdale.com page 20 of 26 issue aj
ml145502, ml145503, ml145505 lansdale semiconductor, inc. v 5 + v 5 + v 5 + v 5 + v 5 + v 5 + v 5 v 5 v 5 + r e k a e p s t e s d n a h o t c n y s l p p u s r e w o py e l a m e f 5 2 b d 7 w s 3 w s p i t r e w o p o t v y l p p u s g n i r 1 4 r 7 3 r n i 7 r 8 r 5 r 6 r 4 r 3 r 2 r 1 r 2 c 3 c 5 c 9 r 3 2 1 6 5 4 9 8 7 * # 0 4 c 0 1 r mc145412 ml145503 mc34119 ml145406 ml145428 mc145426 3 4 5 6 1 5 1 4 1 3 1 8 1 7 v d d v s s 1 c 2 c 3 c 1 r 2 r 3 r 4 r t u o f m t d o s t c s o 4 c c s o s m o m h o l p o 1 9 2 8 0 1 1 1 6 2 1 7 1 5 6 4 6 1 2 3 1 9 i d p c d t c d r e c r d d r d d t e d t v s s 7 2 1 3 1 4 1 5 1 1 1 0 1 8 x t a / i x t o x r + x t v s l v g a v d d 9 c 0 1 c 1 1 c 6 1 r 1 x 7 c 6 c 8 c 5 1 r 1 c 2 1 r 3 1 r 1 1 r 4 1 r 4 3 r 5 3 r 6 3 r 2 x c n 1 w s 2 w s 2 q 5 q 1 q d e l 2 1 c 4 1 c 3 1 c 5 1 c 4 2 r 5 2 r 3 2 r 5 d 4 1 3 2 d c 1 c f 2 c f v n i v 1 o v 2 o v c c d n g 5 8 6 7 1 0 1 1 1 3 1 2 1 4 1 5 1 8 3 x t 3 x r 2 x r 2 x t 1 x t 1 x r d n g v c c v d d v s s 3 i d 3 o d 2 o d 2 i d 1 i d 1 o d 6 1 7 6 4 5 3 2 9 0 2 7 1 4 1 2 1 1 2 1 9 1 5 1 8 1 3 1 s x t k l c r b l d b s 1 r b 2 r b 3 r b k l c b m c v s s 1 4 3 9 6 7 8 5 6 1 0 1 e o d v d d e i d d x t d x r s x r t s r k l c d o c d i c d v d d a / v s s d p 2 2 6 1 1 1 5 1 0 1 0 2 4 1 2 3 5 2 9 8 7 6 7 1 3 1 4 1 8 1 9 1 2 1 2 x 1 x 2 o l b l 1 o l i l d v v f e r 2 o s 2 i s 1 o s 1 i s k l c 1 e t x t x r 1 e r e t o t r e f e r. n o i t a m r o f n i e r o m r o f 8 6 9 n a figure 26. digital telephone schematic k o o h - n o = d e s o l c : 1 w s k o o h - f f o = n e p o www.lansdale.com page 21 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. table 3. mu?aw encode?ecode characteristics chord number step decision decode number of steps size levels sign chord chord chord step step step step levels normalized encode normalized 1 2 3 4 5 6 7 8 digital code 8159 1 0 0 0 0 0 0 0 8031 7903 8 16 256 4319 1 0 0 0 1 1 1 1 4191 4063 7 16 128 2143 1 0 0 1 1 1 1 1 2079 2015 6 16 64 1055 1 0 1 0 1 1 1 1 1023 991 5 16 32 511 1 0 1 1 1 1 1 1 495 479 4 16 16 239 1 1 0 0 1 1 1 1 231 223 3 16 8 103 1 1 0 1 1 1 1 1 99 95 2 16 4 35 1 1 1 0 1 1 1 1 33 31 1 15 2 3 1 1 1 1 1 1 1 0 2 1 1 1 1 1 1 1 1 1 1 1 0 0 notes: 1. characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. digital code includes inversion of all magnitude bits. www.lansdale.com page 22 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. table 4. a?aw encode?ecode characteristics chord number step decision decode number of steps size levels sign chord chord chord step step step step levels normalized encode normalized 1 2 3 4 5 6 7 8 digital code 4096 1 0 1 0 1 0 1 0 4032 3968 7 16 128 2176 1 0 1 0 0 1 0 1 2112 2048 6 16 64 1088 1 0 1 1 0 1 0 1 1056 1024 5 16 32 544 1 0 0 0 0 1 0 1 528 512 4 16 16 272 1 0 0 1 0 1 0 1 264 256 3 16 8 136 1 1 1 0 0 1 0 1 132 128 2 16 4 68 1 1 1 1 0 1 0 1 66 64 1 32 2 2 1 1 0 1 0 1 0 1 1 0 notes: 1. characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. digital code includes alternate bit inversion, as specified by ccitt. www.lansdale.com page 23 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. outline dimensions p dip 16 = ep (ml145503ep, ml145505ep) plastic dip case 648?8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 p dip 22 = wp (ML145502WP) plastic dip case 708?4 min min max max millimeters inches dim 27.56 8.64 3.94 0.36 1.27 1.02 0.20 2.92 28.32 9.14 5.08 0.56 1.78 1.52 0.38 3.43 0 0.51 1.085 0.340 0.155 0.014 0.050 0.040 0.008 0.115 1.115 0.360 0.200 0.022 0.070 0.060 0.015 0.135 15 1.02 2.54 bsc 10.16 bsc 0.100 bsc 0.400 bsc a b c d f g h j k l m n 0 0.020 15 0.040 notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 1 11 12 22 b a l j m n c k seating plane d f g h www.lansdale.com page 24 of 26 issue a
ml145502, ml145503, ml145505 lansdale semiconductor, inc. www.lansdale.com page 25 of 26 issue a plcc 28 = -4p (ml145502-4p) outline dimensions plcc package case 776?2 notes: 1. datums ?? ?? and ??determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum ?? seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). ? ? ? v w d d y brk 28 1 view s s l? s 0.010 (0.250) n s t s l? m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l? m 0.007 (0.180) n s t ? b s l? s 0.010 (0.250) n s t s l? m 0.007 (0.180) n s t u s l? m 0.007 (0.180) n s t z g1 x view d? s l? m 0.007 (0.180) n s t k1 view s h k f s l? m 0.007 (0.180) n s t dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 1.02
ml145502, ml145503, ml145505 lansdale semiconductor, inc. lansdale semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil- ity, function or design. lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. ?ypical?parameters whi ch may be provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including ?ypicals?must be validated for each customer application by the cus- tomers technical experts. lansdale semiconductor is a registered trademark of lansdale semiconductor, inc. www.lansdale.com page 26 of 26 issue a so 16 = -5p (ml145503-5p, ml145505-5p) outline dimensions sog package case 751g?2 dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? ? p 8x g 14x d 16x seating plane ? s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m c k

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